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Buster PLCC

Baustelle

… Gesprächsstoff No.1

Hier werden die PLCC-Varianten besprochen. Die DIP-Version (A2000) auf -> dieser Seite.

Notizen

von Dave Haynie anläßlich einer Auktion zu:
Amiga 3000 Fat Buster 2 Schematics, with notes (März 2015)
This is a schematic for the Rev D of the Fat Buster 2 chip, subtitled „The Chip That Ate New Jersey“. Fat Buster was the Zorro III controller for the Amiga 3000 and 4000 computers. This is a printout from the Commodore laser printer on 17„ x 11“ paper. It's got some notes, and a few circuit changes, that were clearly made by me. I think I was looking at a few of the bus master issues we had on the previous chips. Since CSG didn't revise the font number of the gate array when we went from Fat Buster 1 to Fat Buster 2, so this corresponds to Rev 11 of the packaged part. Rev 9 was the first released version of the Fat Buster 2, Rev 10 basically didn't work (CSG was switching from channeled arrays to sea of gates, and had some issues with delivering a full-speed part). The architecture of the Amiga 3000, in particular Commodore's limit on 84 pins on a package, made this a very tricky part to implement properly. Unfortunately, I designed Zorro III for the next 5-10 years of Commodore systems, not just for the Amiga 3000 in 1990. If I knew that was the end-of-the-road, I might have made it a simpler bus.


Details

TypCommo-Nr. C=Bezeichnung C= Info Form
C390539-07IC FAT BUSTER (25MHZ ONLY)A-3000PLCC84
D390539-09IC FAT BUSTER F013IAMIGA-4000PLCC84
E390539-11IC FAT BUSTER GATE ARRAY AMIGA-4000PLCC84


VorkommenAnzahlPosition Bemerkung
A2631 1 U,Typ D ??
A3000 1 U,Typ C
A3000-T 1 U,Typ
A4000 1 U,Typ
A4000-T 1 U700,Typ E


Pinbelegung Buster PLCC


* = negiert (statt Unterstrich _ geschrieben)

Pin an Signal

FIXME … noch zu klären, ob die Signal-Namen vom A4-T identisch sind, mit denen vom A3000, A3000-T und A4000-Desktop.

PINintern Pin-NameSignal/Route A4-T
1_FCS_FCS
2_CCS_CCS
3A2A_2
4A1A_1
5A0A_0
6RWR_W
7SIZ0SIZ0
8SIZ1SIZ1
9_AS_AS
10_DS_DS
11_DSACK0_CCS
12_DSACK1_DSACK1
13_STERM_STERM
14GND1GROUND
15_RMC_RMC
16_SBR_SBR
17_SBG_SBG
18_CIIN_CIIN
19_MTACK_MTACK
20_DTACKN$55939
21DOEDOE
22_WAIT_WAIT
23_BR_BR
24_BG_BG
25_BGACK_BGACK
26_HLT_HLT
27_BERR_BERR
28GND2GROUND
29_RESET_IORST
30CPUCLKCPUCLKA
31C7ME7M
32_CDACECDAC
33_D2P_D2P
34_DBOE1_DBOE1
35_DBOE0_DBOE0
36_DB16_DBR16
37DBLTDBLT
38READREAD
39_EDS2_EDS2
40_EDS3_EDS3
41EA1EA_1
42VCC1+5V
43_ABOE2_ABOE2
44_ABOE0_ABOE0
45MS2MS_2
46_MTCR_MTCR
47_CACHE_CACHE
48A3A_3
49_CBREQ_CBREQ
50_CBACK_CBACK
51_IOZ2_IOZ2
52_MEMZ2_MEMZ2
53_ADDRZ3_ADDRZ3
54MS1MS_1
55_OWN_OWN
56GND3GROUND
57_EBGACK_EBGACK
58CLK90CLK90A
59_SLAVE4ODDBALL
60EA2EA_2
61EA3EA_3
62_EDS0_EDS0
63_EBCLR_EBCLR
64_SLAVE3_SLAVE_3
65_SLAVE2_SLAVE_2
66_SLAVE1_SLAVE_1
67_SLAVE0_SLAVE_0
68_BIGZ_BIGZ
69_EBG4_EBG_4
70GND4GROUND
71_EBG3_EBG_3
72_EBG2_EBG_2
73_EBG1_EBG_1
74_EBG0_EBG_0
75_ABOE1_ABOE1
76_EBR4_EBR_4
77_EBR3_EBR_3
78_EBR2_EBR_2
79_EBR1_EBR_1
80_EBR0_EBR_0
81MS0MS_0
82_BINT_BINT
83_EDS1_EDS1
84VCC2+5V


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Zuletzt geändert: 2015/03/06 07:20