

Programming of GALs

This document descibes how GALs 16V8/A/B/C/D/Z/ZD, 18V10/B, 20V8/A/B/Z, 
20RA10/B, 20XV10/B, 22V10/B/C/Z, 26CV12/B, 6001/B, and 6002B from Lattice, 
National, and SGS-Thomson can be progammed with minimal effort.

You can find all the data sheets, GAL assemblers easyABEL (DOS) and ISP 
Synario (Windows), PALtoGAL.EXE and a crossref galcross.pdf at
http://www.latticesemi.com, just NO PROGRAMMING SPECS!

(look at http://www.paranoia.com/~filipg/HTML/LINK/F_pal_gal.html).

You need
- socket matching GAL
- some 10k resistors
- 4k7 resistor
- 100nF capacitor
- SubD25 connector
- some 4" short wires
- laboratory power supply 5V and 12-16.5V

The pin out of GALs for programming:
---------------------------------------------------------
                                22V10
                                20XV10  6001
Pin     16V8    18V10   20V8    20RA10  6002    26CV12
1       VIL     VIL     VIL     VIL     VIL     VIL
2       EDIT    EDIT    EDIT    EDIT    EDIT    EDIT
3       RA1     RA3     RA1     P/V     VIL     P/V
4       RA2     RA4     RA2     RA2     RA2     RA2
5       RA3     RA5     RA3     RA1     RA5     RA1
6       RA4     SCLK    VIL     RA0     RA1     RA0
7       RA5     SDIN    VIL     RA3     RA4     VCC
8       SCLK    /STB    RA4     RA4     RA0     VIL
9       SDIN    SDOUT   RA5     RA5     RA3     RA3
10      GND     GND     SCLK    SCLK    SCLK    RA4
11      /STB    VIL     SDIN    SDIN    SDIN    RA5
12      SDOUT   VIL     GND     GND     GND     SCLK
13      VIL     VIL     /STB    /STB    /STB    SDIN
14      VIL     VIL     VIL     SDOUT   SDOUT   /STB
15      VIL     VIL     SDOUT   VIL     VIL     SDOUT
16      VIL     RA0     VIL     VIL     VIL     VIL
17      VIL     RA1     VIL     VIL     VIL     VIL
18      RA0     RA2     VIL     VIL     VIL     VIL
19      P/V     P/V     VIL     VIL     VIL     VIL
20      VCC     VCC     VIL     VIL     VIL     VIL
21                      RA0     VIL     VIL     GND
22                      P/V     VIL     VIL     VIL
23                      VIL     VIL     P/V     VIL
24                      VCC     VCC     VCC     VIL
25                                              VIL
26                                              VIL
27                                              VIL
28                                              VIL
--
PLCC28 pin translation of DIL24 parts see data sheet.

Connect all VIL pins of the GAL socket using 10k resistor to GND to
prevent floating inputs during programming.

Connect SDOUT thru 4k7 with VCC, and put a 100nF cap between
VCC and GND.

Connect GND and VCC (+5V) and GND and EDIT (+12V) with appropriate
outputs of a laboratory power supply. If it does supply only a single
output of 12-16.5V, connect a 7805 between EDIT (IN), GND (GND)
and VCC (OUT).

Connect following pins with the corresponding pin of the SubD25 connector:
--------------------------------------------------------------------------
DB25          GAL
1 (/STB):     /STB
2 (D0):       SDIN 
3 (D1):       RA0
4 (D2):       RA1 
5 (D3):       RA2 
6 (D4):       RA3 
7 (D5):       RA4
8 (D6):       RA5
9 (D7):       SCLK 
10 (/ACK):    SDOUT 
17 (/SELIN):  P/V
25 (GND):     GND
--
The connections are choosen so that an uninitialized port will not affect
the GAL.

Adjust the power supply to 12V. Launch the programming program on the PC
and select the desired LPT port. Place the GAL in the socket and turn on
the power supply, insert the SubD25 into the LPT connector and read the
PES of the GAL. Adjust carfully (without overshoot) the 12V to the
desired VPP voltage, as derived from the PES and program the GAL.
Disconnect SubD25, turn off power and remove the GAL. That's it.

A more elaborate circuit:
Use two 74LS367 powered by 5V to buffer SCLK,RA0..RA5,/STB,P/V,SDIN and
connect /G with pin 14 (/FEED). This pin is normally high and will be
pulled low during accesses from the GAL programmer. Connect SDOUT to a
4k7 pullup and to /G of an unused pair of drivers of the 74LS367. Connect
the input of one of these drivers to GND, the output to pin 17 (/SELIN)
of the LPT port using another 4k7 pullup. This way all GAL connections
are buffered.
 
Use a ZN428 or similar connected to D0..D7 driving a LM358 supplied with
24V to generate VPP. Connect /CLK to pin 16 (/INIT) of the LPT port,
becaue the GAL programmer will output the desired programming voltage
in 0.125V increments on D0..D7 and assert /INIT prior to programming.
VCC of the GAL may be controlled using /FEED (active L) and can drive
an LED signalling 'in use'.

          2*74LS367
               +----------+
              /G          |                            +5V+5V
1 (/STB) -----|>--- /STB  |             16 (/INIT) -+   |  |
17 (/SELIN) --|>--- P/V   |                         |   | 390R
                          |                        +-----+ |
2 (D0) -------|>--- SCLK  |               2 (D0) --|     |-+
3 (D1) -------|>--- RA0   |   +5V+5V      3 (D1) --|     |-+--10uF-- GND
4 (D2) -------|>--- RA1   |    |  |       4 (D2) --|     |
5 (D3) -------|>--- RA2   |   4k7 |       5 (D3) --|ZN428|   |\ (VCC to 24V)
              /G          |    |  | E     6 (D4) --|     |---|+\ LM358
14 (/FEED) ----+----------+-1k-+-|<BC327  7 (D5) --|     |   |  >-+-- EDIT
              /G                B | C     8 (D6) --|     | +-|-/  |    GAL
6 (D4) -------|>--- RA3           |       9 (D7) --|     | | |/   |
7 (D5) -------|>--- RA4          VCC               +-----+ +-110k-+
8 (D6) -------|>--- RA5          GAL                  |    |
9 (D7) -------|>--- SDIN                             GND  10k
                                                           |
10 (/ACK) -+--<|-GND                                      GND
           |  /G                  IN +-------+ OUT
           |   +-+- SDOUT     24V -+-| 7805  |-+-- +5V
          4k7   4k7                | +-------+ |
           |     |                47uF   |    100nF
          +5V   +5V                +----GND----+

If you like to write the software yourself:

Init
Set all outputs of the LPT port to L, except /STB which should be H.
Take care of negated outputs.

Reading  (16V8/20V8) at VPP 12 Volt:
Set up the desired row address to RA0..RA5, pull /STB to L shortly and back
to H, read bit from SDOUT and pull SCLK shortly to H (1-10us) and back to L
and read the next bit until all bits of this row are read.

Reading (other) at VPP 12 Volt:
Set up the desired row address to RA0..RA5, set up the first bit (a L for
fuses, else H or L for column address as specified) on SDIN, pull SCLK
shortly (1- 10us) to H and back to L and transfer next bit until all bits
of this row are transferred, pull /STB to L shortly (1-10us) and back to H,
read bit from SDOUT and pull SCLK shortly to H (1-10us) and back to L and
read the next bit until all bits of this row are read.

Write, erase, burn security fuse (all) at VPP Volt:
Set P/V to H, set up the desired row address to RA0..RA5, set up the first
bit on SDIN, pull SCLK shortly (1-10us) to H and back to L and transfer
next bit until all bits of this row are transferred. Pull /STB to L, wait
the programming time, take /STB back to H and restore P/V to L at end.

Format of PES, needed to derive programming voltage and pulse duration:

16V8D: 00 05 1A A1 4D A5 03 06

b0(LSB)..b7(MSB)=Byte B0=# of programming cycles (if specified)
b8..b14=Byte B1=programming algorithm, dependend on GAL type

   16V8 20RA10
   20V8 20XV10
   6001 22V10
   6002 18V10
        26CV12
    00   01    VPP 15.75V programming pulse 100ms
    01         VPP 15.75V programming pulse 80ms
    02   00    VPP 16.50V programming pulse 10ms
    03   02    VPP 14.50V (National 15.00V) programming pulse 40ms
    04   03    VPP 14.00V programming pulse 100ms
    05   05    definitions stored at bit 32 (D4)

b15=MASTER bit (erase/reprogram GAL only after query if set)
b16..b23=Byte B2=GAL type

   0x00=16V8
   0x1A=16V8A/B/C/D/Z/ZD
   0x20=20V8
   0x3A=20V8A/B/Z
   0x40=6001
   0x41=6001B
   0x44=6002B
   0x48=22V10
   0x49=22V10B/C/Z
   0x50=18V10
   0x51=18V10B
   0x58=26CV12
   0x59=26CV12B
   0x60=20RA10
   0x61=20RA10B
   0x65=20XV10
   0x66=20XV10B

b24..b31=Byte B3=manufacturer

   0xA1=Lattice
   0x8F=National
   0x20=SGS-Thomson

The following bits are only valid for programming algorithm 5:
b32..b35: erase time 10,25,50,100,200,400,800,- msec (only if B1=0x05),
else
   for 6001, 6002, National 20RA10, 20XV10, 22V10, 18V10, 26V12: 50 msec, 
   else 100 msec
b36..b39: programming pulse 1,2,5,10,20,30,40,50,60,70,80,90,100,200,-,-
msec
b40..b44: VPP(program) 5.0,5.5,6.0,...20.5V
b45..b49: VPP(erase) 5.0,5.5,6.0,...20.5V
b56..b63: checksum

To transfer the fuses, you need to know the internal organisation of the
GAL. The GAL data sheet will show you the JEDEC fuse number, here the
numbers 0-xxx, H and L are constant address bits and b0..bxxx are the
bits of the PES.

The leftmost bit is the first to shift into the GAL and the first returned
on reading, RA is the row addresss set up on RA0..RA5. CLEARALL does also
erase the PES, CLEAR anything except the PES. '-' denotes a increasing
or decreasing run of fuse numbers, '...' or vertically ':' denotes
repetition in the displacement of both of the previous values up to the
following value, '*' denotes n-times the same value.

GAL16V8 (0x00):
Fusemap: RA=0:  0,32,...2016 (64 bit)
         RA=1:  1,33,...2017 (64 bit)
                 :
         RA=31: 31,63,...2047 (64 bit)
UES:     RA=32: 2056-2119 (64 bit)
PES:     RA=58: b0..b63 (64 bit)
CFG:     RA=60: 2191-2160,2055-2052,2192,2127-2120,2193,2051-2048,2159-2128

                (82 bit)
CLEAR:   RA=63: H (1 bit)
CLEARALL:RA=62: H (1 bit) ; oder 57
SECURITY:RA=61: H (1 bit)

GAL16V8A/B (0x1A) like 16V8 except:
CFG:     RA=60: 2055-2052,2192,2127-2124,2191-2128,2123-2120,2193,2051-2048

                (82 bit)

GAL18V10 (0x50,0x51):
Fusemap: RA=0:  0,36,...3420,L,L,L,L,L,L (96+6 bit, line 0)
         RA=0:  1,37,...3421,H,L,L,L,L,L (96+6 bit, line 1)
                 :
         RA=0:  35,68,...3455,H,H,L,L,L,H (96+6 bit, line 35)
UES:     RA=0:  3476-3539,32*L,L,L,H,L,L,H (64+32+6 bit, line 36)
PES:     RA=0:  b0..b79,16*L,L,H,L,H,H,H (80+16+6 bit, line 58)
CFG:     RA=16: 3457,3456,3459,3458,...3475,3474 (20 bit)
CLEAR:   RA=61: (0 bit)
CLEARALL:RA=57: (0 bit)
SECURITY:RA=0:  96*L,H,L,H,H,H,H (96+6 bit, line 61)

GAL20V8 (0x20):
Fusemap: RA=0:  0,32,...2528 (80 bit)
         RA=1:  1,33,...2529 (80 bit)
                 :
         RA=31: 31,63,...2559 (80 bit)
UES:     RA=32: 2568-2631 (64 bit)
PES:     RA=58: b0..b63 (64 bit)
CFG:     RA=60: 2703-2672,2567-2564,2704,2639-2632,2705,2563-2560,2671-2640

                (82 bit)
CLEAR:   RA=63: H (1 bit)
CLEARALL:RA=57: H (1 bit)
SECURITY:RA=61: H (1 bit)

GAL20V8A/B (0x3A) like 20V8 except:
CFG:     RA=60: 2560-2564,2704,2639-2636,2703-2640,2635-2632,2705,2564-2567

                (82 bit)

GAL20RA10 (0x60,0x61):
Fusemap: RA=0:  0,40,...3080,L,L,L,L,L,L (80+6 bit, line 0)
         RA=0:  1,41,...3081,H,L,L,L,L,L (80+6 bit, line 1)
                 :
         RA=0:  39,79,...3119,L,L,H,L,L,H (80+6 bit, line 39)
UES:     RA=0:  3210-3273,16*L,L,L,L,H,L,H (64+16+6 bit, line 40)
PES:     RA=0:  b0..b79,L,H,L,H,H,H (80+6 bit, line 58)
CFG:     RA=16: 3200-3209 (10 bit)
CLEAR:   RA=61: (0 bit)
CLEARALL:RA=57: (0 bit)
SECURITY:RA=0:  80*L,H,L,H,H,H,H (80+6 bit, line 61)

GAL20XV10 (0x65,0x66):
Fusemap: RA=0:  0,40,...1560,L,L,L,L,L,L (40+6 bit, line 0)
         RA=0:  1,41,...1561,H,L,L,L,L,L (40+6 bit, line 1)
                 :
         RA=0:  39,79,...1599,H,H,L,H,L,H (40+6 bit, line 39)
UES:     RA=0:  1631-1670,L,L,H,H,L,H (40+6 bit, line 40)
PES:     RA=0:  b0..b39,L,H,L,H,H,H (40+6 bit, line 58)
         RA=0:  b40..b79,H,H,L,H,H,H (40+6 bit, line 59) (???!!!???)
CFG:     RA=16: 1630,1628,1629,1620-1622,1610-1614,1600-1604,1627,1626,
                1623-1625,1619-1615,1609-1605 (31 bit)
CLEAR:   RA=61: (0 bit)
CLEARALL:RA=57: (0 bit)
SECURITY:RA=0:  40*L,H,L,H,H,H,H (40+6 bit, line 61)

GAL22V10 (0x48,0x49):
Fusemap: RA=0:  0,44,88,...5764,L,L,L,L,L,L (132+6 bit, line 0)
         RA=0:  1,45,89,...5765,H,L,L,L,L,L (132+6 bit, line 1)
                 :
         RA=0:  43,87,131,...5807,H,H,L,H,L,H (132+6 bit, line 43)
UES:     RA=0:  5828-5891,68*L,L,L,H,H,L,H (64+68+6 bit, line 44)
PES:     RA=0:  b0..b79,52*L,L,H,L,H,H,H (80+52+6 bit, line 58)
CFG:     RA=16: 5809,5808,5811,5810,...5827,5826 (20 bit)
CLEAR:   RA=61: (0 bit)
CLEARALL:RA=57: (0 bit)
SECURITY:RA=0:  132*L,H,L,H,H,H,H (132+6 bit, line 61)

GAL26CV12 (0x58,0x59):
Fusemap: RA=0:  0,52,...6292,L,L,L,L,L,L (122+6 bit, line 0)
         RA=0:  1,53,...6293,H,L,L,L,L,L (122+6 bit, line 1)
                 :
         RA=0:  51,103,...6343,H,H,L,L,H,H (122+6 bit, line 51)
UES:     RA=0:  6368-6431,58*L,L,L,H,L,H,H (64+58+6 bit, line 52)
PES:     RA=0:  b0..b95,26*L,L,H,L,H,H,H (96+26+6 bit, line 58)
CFG:     RA=16: 6345,6344,6347,6346,...6367,6366 (24 bit)
CLEAR:   RA=61: (0 bit)
CLEARALL:RA=57: (0 bit)
SECURITY:RA=0:  122*L,H,L,H,H,H,H (122+6 bit, line 61)

GAL6001 (0x40,0x41):
Fusemap: RA=0:  20*L,7296,7374,...8076,
0,114,...7182,1*H,L,L,L,L,L,L,L,16*L 
                (119 bit, line 0)
         RA=0:  20*L,7297,7375,...8077,
1,115,...7183,1*H,H,L,L,L,L,L,L,16*L 
                (119 bit, line 1)
                 :
         RA=0: 
20*L,7373,7451,...8153,77,191,...7259,1*H,H,L,H,H,L,L,H,16*L 
                (119 bit, line 77)
         RA=0:    78-  97,11*L,63*L,H, 0*L,8*L,  98- 113 (119 bit, column
0)
         RA=0:   192- 211,11*L,62*L,H, 1*L,8*L, 212- 227 (119 bit, column
1)
                 :            (1 of 64 set)
         RA=0:  7260-7279,11*L, 0*L,H,63*L,8*L,7280-7295 (119 bit, column
63)
UES:     RA=0:  20*L,8222-8293,3*L,1*H,H,L,L,L,L,H,H,16*L (119 bit, line
97)
CFG:     RA=16:
8221,8220,8179,8183,8187,...8215,8214,8210,...8178,8216,8217,
               
8212,8213,8208,8209,8204,8205,8200,8201,8196,8197,8192,8193,
               
8188,8189,8184,8185,8180,8181,8156,8159,...8177,8154,8157,...
                8175,8176,8173,...8155,8218,8219 (68 bits)
PES:     RA=0:  20*L,b0..b63,11*L,1*H,L,L,L,L,L,H,H,16*L (119 bit, line 96)
CLEAR:   RA=63: (0 bit)
CLEARALL:RA=59: (0 bit)
SECURITY:RA=0:  95*L,1*H,L,H,L,L,L,H,H,16*L (119 bit, line 98)

GAL6002 (0x44) wie 6001 bis auf:
UES:     RA=0:  20*L,8258-8329,3*L,1*H,H,L,L,L,L,H,H,16*L (119 bit, line
97)
CFG:     RA=16: 8257,8256,8179,8183,...8215,8214,8210,...8178,8216,8217,
               
8212,8213,8208,8209,8204,8205,8200,8201,8196,8197,8192,8193,
               
8188,8189,8184,8185,8180,8181,8255,8254,8251,8250,8247,8246,
               
8243,8242,8239,8238,8235,8234,8231,8230,8227,8226,8223,8222,
               
8220,8221,8224,8225,8228,8229,8232,8233,8236,8237,8240,8241,
               
8244,8245,8248,8249,8252,8253,8156,...8177,8154,8157,...8175,
                8176,8173,...8155,8218,8219 (104 bit)

That's it what I have collected so far. Hopefully no errors & mistakes.
Hope you don't mind my bad english translation. 


